Below is a fix for the dynamic recompiler for RISC OS 5 - basically it
stops spurious 'bad SWI' errors when dragging files, running !Blocks
etc. What's happening is that R15 is loaded with an address with the
bottom two bits set. Normally that's fine and they're ignored. However
when this is used as the index to a SWI instruction the SWI number the
handlers get is rotated and you get some nice crashes.

My fix is to just force the bottom two bits low on exit from a
recompiled block (as blocks end when R15 changes other than from a
branch - which is always aligned). I suppose you could just alter the
value put in R14 on an exception, but this is potentially more
compatible as otherwise an STR/STM R15 would store an incorrect value.
The real fix would be to find where R15 is loaded in the dynarec and
mask the value there, but I'm too lazy at the minute to do that.

diff -r 4697ed76d1b7 src/ArmDynarec.c
--- a/src/ArmDynarec.c	Sun Jun 20 13:51:58 2010 +0100
+++ b/src/ArmDynarec.c	Thu Jun 24 14:09:12 2010 +0100
@@ -740,6 +740,7 @@
 //                                        gen_func=(void
*)(&codeblock[blocks[templ]>>24][blocks[templ]&0xFFF][4]);
                                         gen_func();
                                         if (armirq&0x40) armregs[15]+=4;
+                                        if (mode&16) armregs[15]&=~3;
                                         if
((armregs[cpsr]&mmask)!=mode) updatemode(armregs[cpsr]&mmask);
                                 }
                                 else

---------------------------------

Notes added by Peter,

to track bug add an if into the code in ArmDynarec that checks for bottoms two
bits high and it being a SWI instruction and it being in the correct processor
mode, stick a breakpoint on it, and run !Blocks. That should give a backtrace,
which hopefully should help in tracking it down.